? semiconductor components industries, llc, 2002 march, 2002 rev. 1 1 publication order number: nbsg14/d nbsg14 2.5v/3.3vsige differential 1:4 clock/data driver with rsecl* outputs *reduced swing ecl the sg14 is a silicon germanium 1to4 clock/data distribution chip, optimized for ultralow skew and jitter. inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), ttl, cmos, cml, or lvds. outputs are rsecl (reduced swing ecl), 400 mv. ? maximum input clock frequency up to 12 ghz (see figure 3) ? 30 ps typical rise and fall times ? 125 ps typical propagation delay ? rspecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? rsnecl output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = 2.375 v to 3.465 v ? rsecl output level (400 mv peaktopeak output), differential output ? 50 internal input termination resistors ? compatible with existing 2.5 v/3.3 v lvep, ep, and lvel devices l = wafer lot y = year w = work week *for further details, refer to application note and8002/d fcbga16 ba suffix case 489 marking diagram* sg 14 device package shipping ordering information nbsg14ba 4x4 mm fcbga16 100 units/tray nbsg14bar2 4x4 mm fcbga16 500/tape & reel lyw board description sg14evb nbsg14ba evaluation board http://onsemi.com
nbsg14 http://onsemi.com 2 vtclk, vtclk pin description pin clk*, clk ** q0:3, q0:3 rsecl data outputs function ecl, ttl, cmos, cml, lvds compatible inputs v cc positive supply v ee negative supply 50 internal input termination resistor 50 * pin will default low when left open. ** pin will default to a higher potential than clk when vtclk/vtclk and clk/clk are left open. figure 1. pinout (top view) vtclk clk clk vee vtclk q0 vee q3 q3 q2 vcc vcc q0 q1 q1 q2 a b c d 12 34 50 (a1) vtclk (b1) clk (c1) clk (d1) vtclk v ee (b2, c2) v cc (b3, c3) figure 2. logic diagram 75 k 75 k 36.5 k q3 (a2) q3 (a3) q2 (a4) q2 (b4) q1 (c4) q1 (d4) q0 (d3) q0 (d2) interfacing options interfacing options connections cml connect vtclk and vtclk to v cc lvds connect vtclk and vtclk together accoupled bias vtclk and vtclk inputs within common mode range (v ihcmr ) rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos an external voltage (v thr ) should be applied to the unused differential input. nominal v thr is 1.5 v for lvttl and v cc /2 for lvcmos inputs. this voltage must be within the v thr specification.
nbsg14 http://onsemi.com 3 attributes characteristics value internal input pulldown resistor (clk, clk ) 75 k w internal input pullup resistor (clk ) 36.5 k w esd protection human body model machine model > 2 kv > 100 v moisture sensitivity (note 1) level 3 flammability rating ul 94 v0 @ 0.125 in oxygen index 28 to 34 transistor count 158 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v 3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 3.6 v v v inpp (inin) differential input voltage (|clkclk |) v cc v ee 2.8 v v cc v ee < 2.8 v 2.8 |v cc v ee | v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range 40 to +70 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) (note 3) 0 lfpm 500 lfpm 16 fcbga 16 fcbga 108 86 c/w c/w q jc thermal resistance (junctiontocase) 2s2p (note 3) 16 fcbga 5 c/w t sol wave solder < 15 seconds 225 c 2. maximum ratings are those values beyond which device damage may occur. 3. jedec standard 516, multilayer board 2s2p (2 signal, 2 power).
nbsg14 http://onsemi.com 4 dc characteristics, input with rspecl output v cc = 2.5 v; v ee = 0 v (note 4) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 5) 1525 1575 1625 1550 1610 1650 1575 1635 1675 mv v outpp output pp voltage 315 405 495 315 405 495 315 405 495 mv v ih input high voltage (singleended) (notes 7 and 9) v cc 1435 v cc 1000* v cc v cc 1435 v cc 1000* v cc v cc 1435 v cc 1000* v cc mv v il input low voltage (singleended) (notes 8 and 9) v ih 2500 v cc 1400* v ih 150 v ih 2500 v cc 1400* v ih 150 v ih 2500 v cc 1400* v ih 150 mv v thr input threshold voltage (singleended) (note 9) v ee + 1125 v cc 75 v ee + 1125 v cc 75 v ee + 1125 v cc 75 mv v ihcmr input high voltage common mode range (differential) (note 6) 1.2 2.5 1.2 2.5 1.2 2.5 v r t internal termination resistor 45 50 55 45 50 55 45 50 55 w i ih input high current (@ v ih ) 30 100 30 100 30 100 m a i il input low current (@ v il ) 25 100 25 100 25 100 m a note: sige circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to 0.5 v. 5. all outputs loaded with 50 w to v cc 1.5 volts. v oh /v ol measured at v ih /v il (typical). 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 7. v ih cannot exceed v cc . |v ih v thr | < 2600 mv. 8. v il always v ee . |v il v thr | < 2600 mv. 9. v thr is the voltage applied to one input when running in singleended mode. *typicals used for testing purposes. dc characteristics, input with rspecl output v cc = 3.3 v; v ee = 0 v (note 10) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 11) 2325 2375 2425 2350 2410 2450 2375 2435 2475 mv v outpp output pp voltage 350 440 530 350 440 530 350 440 530 mv v ih input high voltage (singleended) (notes 13 and 15) v cc 1435 v cc 1000* v cc v cc 1435 v cc 1000* v cc v cc 1435 v cc 1000* v cc mv v il input low voltage (singleended) (notes 14 and 15) v ih 2500 v cc 1400* v ih 150 v ih 2500 v cc 1400* v ih 150 v ih 2500 v cc 1400* v ih 150 mv v thr input threshold voltage (singleended) (note 15) v ee + 1125 v cc 75 v ee + 1125 v cc 75 v ee + 1125 v cc 75 mv v ihcmr input high voltage common mode range (differential) (note 12) 1.2 3.3 1.2 3.3 1.2 3.3 v r t internal termination resistor 45 50 55 45 50 55 45 50 55 w i ih input high current (@ v ih ) 30 100 30 100 30 100 m a i il input low current (@ v il ) 25 100 25 100 25 100 m a note: sige circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 0.165 v. 11. all outputs loaded with 50 w to v cc 1.5 volts. v oh /v ol measured at v ih /v il (typical). 12. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 13. v ih cannot exceed v cc . |v ih v thr | < 2600 mv. 14. v il always v ee . |v il v thr | < 2600 mv. 15. v thr is the voltage applied to one input when running in singleended mode. *typicals used for testing purposes.
nbsg14 http://onsemi.com 5 dc characteristics, necl or rsnecl input with necl output v cc = 0 v; v ee = 3.465 v to 2.375 v (note 16) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 17) 975 925 875 950 890 850 925 865 825 mv v outpp output pp voltage 3.465 v v ee 3.0 v 3.0 v < v ee 2.375 v 350 315 440 405 530 495 350 315 440 405 530 495 350 315 440 405 530 495 mv v ih input high voltage (singleended) (notes 19 and 21) v cc 1435 v cc 1000* v cc v cc 1435 v cc 1000* v cc v cc 1435 v cc 1000* v cc mv v il input low voltage (singleended) (notes 20 and 21) v ih 2500 v cc 1400* v ih 150 v ih 2500 v cc 1400* v ih 150 v ih 2500 v cc 1400* v ih 150 mv v thr input threshold voltage (singleended) (note 21) v ee + 1125 v cc 75 v ee + 1125 v cc 75 v ee + 1125 v cc 75 mv v ihcmr input high voltage common mode range (differential) (note 18) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v i ih input high current (@ v ih ) 30 100 30 100 30 100 m a i il input low current (@ v il ) 25 100 25 100 25 100 m a note: sige circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 16. input and output parameters vary 1:1 with v cc . 17. all outputs loaded with 50 w to v cc 1.5 volts. v oh /v ol measured at v ih /v il (typical). 18. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 19. v ih cannot exceed v cc . |v ih v thr | < 2600 mv. 20. v il always v ee . |v il v thr | < 2600 mv. 21. v thr is the voltage applied to one input when running in singleended mode. *typicals used for testing purposes. ac characteristics v cc = 0 v; v ee = 3.465 v to 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 3) (note 22) 10.7 (note 27) 12 10.7 (note 27) 12 10.7 (note 27) 12 ghz t plh , t phl propagation delay to output differential 100 125 150 100 125 150 100 125 150 ps t skew duty cycle skew (note 23) withindevice skew (note 24) devicetodevice skew (note 25) 2 6 25 10 15 50 2 6 25 10 15 50 2 6 25 10 15 50 ps t jitter cycletocycle jitter (rms) (see figure 3) (note 22) 0.5 1 0.5 1 0.5 1 ps v inpp input voltage swing/sensitivity (differential) (note 26) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times q, q (20% 80%) 20 30 55 20 30 55 20 30 55 ps 22. measured using a 500 mv source, 50% duty cycle clock source. all outputs loaded with 50 w to v cc 1.5 v. 23. see figure 5. t skew = |t plh t phl | for a nominal 50% differential clock input waveform. 24. withindevice skew is measured between outputs under identitical transitions and conditions on any one device. 25. devicetodevice skew for identical transitions at identical v cc levels. 26. v inpp (max) cannot exceed v cc v ee (applicable only when v cc v ee < 2600 mv). 27. conditions include input amplitude of 500 mv. minimum output amplitude guarantee of 100 mv (see output pp spec in figure 3) .
nbsg14 http://onsemi.com 6 ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ??????? ??????? output pp spec (amplitude guarantee) figure 3. v out /jitter vs. frequency (v cc v ee = 3.3v @ 25 c) 0 100 200 300 400 500 123456789101112 frequency (ghz) v outpp (mv) jitterout ps (rms) ???? ???? rms jitter 1 2 3 4 5 6 7 8 9 10 0 output amplitude figure 4. eye diagram at 10.8 gbps (v cc v ee = 3.3 v @ 25 c with input data pattern of 2^311 prbs. total pkpk system jitter including signal generator is 18 ps. this data was taken by acquiring 7000 waveforms.) x = 17 ps/div, y = 53 mv/div
nbsg14 http://onsemi.com 7 receiver device driver device q q d d 50 w 50 w v tt v tt = v cc 1.5 v t phl figure 5. ac reference measurement d /clk d/clk q q t plh v pp figure 6. typical termination for output driver and device evaluation (refer to application note and8020 termination of ecl logic devices)
nbsg14 http://onsemi.com 8 package dimensions fcbga16 ba suffix plastic 4x4 (mm) bga flip chip package case 48901 issue o 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.10 z 0.15 z rotated 90 clockwise detail k 5 view mm e 3 x s m x 0.15 y z 0.08 z 3 b 16 x feducial for pin a1 identification in this area 4321 a b c d 4 16 x notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.40 max a1 0.25 0.35 a2 1.20 ref b 0.30 0.50 d 4.00 bsc e 4.00 bsc e 1.00 bsc s 0.50 bsc k x y m m z on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nbsg14/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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